In present, because of high image quality, small size, light weight, wide application range and so on, flat panel displays such as liquid crystal displays (LCDs) are broadly employed in mobile phones, notebook computers, desktop computers, televisions and other consumer electronic products, and gradually replace traditional cathode ray tube (CRT) displays to become mainstream displays.
Referring to FIGS. 1A and 1B, FIG. 1A is a schematic configuration of a gate driving circuit employed in a display panel with charge sharing pixel structure and waveforms of driving pulses outputted from the gate driving circuit in a single frame F(m), and FIG. 1B is a schematic circuit diagram of a single pixel.
As shown in FIG. 1A, the gate driving circuit includes a charging gate driving unit string and a sharing gate driving unit string. The charging gate driving unit string includes cascade-connected charging gate driving units Ch[1]-Ch[n] and dummy charging gate driving units Ch[DM1]-Ch[DM4]. The sharing gate driving unit string includes cascade-connected delay sharing gate driving units SR[DMA]-SR[DMB], sharing gate driving units SR[1]-SR[n] and dummy sharing gate driving units SR[DM1]-SR[DM4]. The charging gate driving unit string receives a start pulse ST and generates output pulses stage by stage, thereby the charging gate driving units Ch[1]-Ch[n] sequentially output charging gate driving pulses G(1)-G(n) to determine whether corresponding pixels receive display data from data lines. When the sharing gate driving unit string receives the start pulse ST, the start pulse ST is firstly delivered by the delay sharing gate driving units SR[DMA]-SR[DMB], and then delivered to each of the sharing gate driving units SR[1]-SR[n] for sequentially outputting sharing gate driving pulses S(1)-S(n) to determine whether the corresponding pixels internally share charges.
Regarding multiple pixels driven by the charging gate driving unit string and the sharing gate driving unit string, as shown in FIG. 1B, each of the pixels includes a secondary sub-pixel 101 and a main sub-pixel 103. A pixel transistor M1 of the secondary sub-pixel 101 is electrically coupled to a gate line such as GL(n) and a data line such as DL(q) and thereby subjected to the control of a charging gate driving pulse G(n) to determine on-off states thereof. A pixel transistor M2 of the main sub-pixel 103 is electrically coupled to the same gate line GL(n) and the same data line DL(q) and thereby subjected to the control of the charging gate driving pulse G(n) to determine on-off states thereof. Furthermore, the pixel transistor M2 of the main sub-pixel 103 is electrically coupled to the secondary sub-pixel 101 via a sharing transistor M3. The sharing transistor M3 is electrically coupled to a sharing control line such as SGL(n) and thereby subjected to the control of a sharing gate driving pulse S(n) to determine on-off states thereof. Therefore, when the sharing transistor M3 is turned on, the secondary sub-pixel 101 and the main sub-pixel 103 mutually share for improving color washout phenomenon appeared under large viewing angle.
Referring again to FIG. 1A, each stage of the charging gate driving units for example the charging gate driving unit Ch[n−2] is subjected to the control of the charging gate driving pulse G(n) outputted from the second succeeding-stage charging gate driving unit Ch[n] thereof to determine the time of stopping outputting the charging gate driving pulse G(n−2). However, the backward-extended wire for delivering the charging gate driving pulse G(n) from the charging gate driving unit Ch[n] to the charging gate driving unit Ch[n−2] is arranged crossing multiple stages of charging gate driving unit and sharing gate driving unit, which not only needs excessively much wire layout space but also consumes much power. Furthermore, the increase of parasitic resistance and capacitance caused by the backward-extended wire would deteriorate the output waveform of the current stage charging gate driving unit Ch[n−2].